A focal plane detector array comprises numerous detector unit cells or pixels, each of which converts incident electromagnetic radiation to an electric signal. The unit cells output an analog signal corresponding to scene radiation sensed by the particular detector element. These analog signals must be converted to digital in order to be combined and efficiently processed to resolve an image of a scene being viewed by the array of detector elements. It is noted that focal plane detector arrays are disposed within a temperature-controlled chamber to minimize localized heat that might otherwise interfere with the intended scene radiation as noise. Excessive power dissipation, such as by power inefficient amplifiers and ADCs mounted in or near the chamber, places an additional burden on the Dewar or thermoelectric cooling elements that are employed for regulating chamber temperature. The particular aspects of prior art ADCs and an improved (single slope) ADC are detailed in the related application cross-referenced above.
The ADC of the incorporated reference is within that class of ADCs termed single slope. In general, a single slope ADC operates on the following principle. An internal (voltage) ramp is generated to begin the conversion from analog, and a counter is enabled to count pulses from a stable clock. When the ramp voltage equals a trip of input level, a comparator stops the counter. The output of the counter is proportional to the input level, but is digital. At the end of the conversion the ramp resets (such as by discharging an integrating capacitor), resets the counter, and another cycle begins.
While single slope ADCs are relatively simple, they are traditionally not used where high accuracy is required because they are limited by the stability and accuracy of the capacitor and comparator. Traditionally, dual slope or other types of ADCs have been used to overcome the precision problem of single slope ADCs rather than use very high quality capacitors and comparators in the single slope solution. Dual slope ADCs have traditionally proven more cost effective and more precise. However, they are not quite as fast as single slope ADCs.
In the field of electronic imaging, such as thermal or IR sensing by a multitude of arrayed detector elements whose individual signals are combined into a comprehensive image for display or electronic analysis, speed and power are important considerations. Circuit speed is necessary for real-time imaging at high resolution. Low power is important for two reasons: to protect the detectors themselves from excessive heat, and to enable imaging with portable power. As to the former, the sensitivity of the detectors typically relies on the photosensitive field to lie within a chamber that is highly temperature controlled, in order that thermal noise not be sensed as the desired scene radiation. This is true for both cryogenic and non-cryogenic detectors. As to the latter, there is an increasing need for mobile imaging systems that rely on DC power (battery, fuel cell), especially in military applications such as unmanned aerial vehicles and night imaging equipment for individual soldiers. In the prior art, the predominant approach was to keep circuitry at the level of the individual detector element simple and perform signal-processing off-chip after combining signals from the various detector elements.
However, processing the signals after they are combined is greatly complicated over processing them individually at the level of the detector elements. Because there are typically thousands of detector elements in a single arrayed device, any circuitry at the detector element level implies that its element-level cost is multiplied by the number of elements in the array for an overall detector device. This balancing of cost versus signal-processing efficiency has weighed in favor of more complex signal processing in the past. One factor against processing at the detector element level is that the signals from the detector elements may vary over a broad range, leaving a tradeoff between simplicity and accuracy.
Related art that provides more context for the present invention includes the following co-owned patents: U.S. Pat. No. 5,751,005 to Wyles et al. and entitled “Low Crosstalk Column Differencing Circuit Architecture for Integrated Focal Plane Arrays; U.S. Pat. No. 6,040,568 to Caulfield et al. and entitled “Multipurpose Readout Integrated Circuit with In Cell Adaptive Non-Uniformity Correction and Enhanced Dynamic Range”; and also U.S. Pat. No. 6,587,001 to Wyles et al. and entitled “Analog Load Driver”. As will be seen, these patents are not directed toward solving the specific problems addressed by the present invention.
The present invention represents one element in a solution to perform more signal processing at the level of the individual detector elements, or the unit cells, of an imaging array. It is particularly developed to be used in conjunction with that co-pending application that is cross-referenced and incorporated above.